In semiconductor manufacturing, an automatic test equipment (ATE) is used to test integrated circuit (IC) devices (known as the Devices Under Test (DUTs)) e.g., to characterize electrical properties, detect abnormalities, and evaluate product quality. During test operations, test signals are provided to the DUT and the resultant output signals generated from the DUT are evaluated against expectation values.
FIG. 1 illustrates the configuration of an IC device 110 and the timing diagrams in a scan test performed on an ATE. For example, the scan test may implement a stuck-at or delay test scan application. Pertinent to the scan test, the IC device 110 includes parallel input/output (IO) pins 101, combinational logic 103, and scan chain flip-flops (scan chain FF) 105.
During the scan shift phase in the scan test, the scan data is shifted into the scan chain flip flops (scan chain-FF) 105 through scan shift cycles 121. At the same time, the scan data of the previous shift phase is shifted out of the scan chain FF 105. After all data has been shifted in, a system clock pulse 122 (“launch clock”) triggers releasing of the scan data from the flip flops 105. The data propagates through the combinational logic 103 to the input of scan-FF 105. A second clock pulse 123 (“capture clock”) triggers capturing the data into the scan-FF 105. Regarding the data communication between the DUT and the tester, a capture clock (as shown) is used to latch-in data from the tester into the DUT; while during a launch clock phase (as shown) a tester strobe edge is used to latch-in data coming from the DUT into the tester
The combinational logic 103 on the outer side of the device 110 may or may not be surrounded by scan-FF. In case they are not, the data are supplied from the associated tester system (not shown) through the device parallel IO pins 101 prior to the Capture clock 123 by a setup time (Tsu).
Similar for the data which comes out of the combinational logic 103, the data are “strobed” into the ATE system channels (or tester channels) after the Launch clock 122 by a propagation delay time (Tpd), which are connected to the parallel IO 101 pads of the device 110.
To keep up with the increasing demands for higher throughput of IC devices, state-of-the-art ATEs have to be equipped with sufficient test channels for coupling to the parallel IO pins of the DUTs. This contributes to substantial capital cost of overall cost of the test system and device production. For example, relatively large digital devices typically have 100-400 input/output (I/O) pins. However, most of these IO pins are only utilized in about 20% of the overall test blocks. Adding tester channels for all these IO pins would translate into high additional capital cost for test equipments even though utilization of these pins is rather low.
Another solution for overcoming the ATE test channel limitation is to multiplex the parallel IO pins of a DUT to the ATE test channels in scan tests. FIG. 2 illustrates multiplexing configuration between a DUT 210 and a test system 220 (or “tester”) and a scan test sequence 240 of a multiplexing scan test in accordance with the prior art. The test system 220 may provide fewer test channels 221 than the primary IO pins of the DUT 210. As shown, the DUT pins 203 and 204 are used for scan-in and scan-out and connected to the test system 220 without using a multiplexer. The DUT primary parallel IO pins are divided into two groups 201 and 202, both groups coupled to a single test site of the test system 220 through a 2:1 multiplexer 230. The multiplexer 230 is normally located on the test load board (adapter board between device and test system).
In this configuration, a scan test for the device needs to be performed twice in order for the tester 220 to collect all the device response data from both groups of IO pins 201 and 202. This is because the capture clock occurs only once in a scan shift in/out phase.
Specifically, in the first test execution, as illustrated in diagram 250, the multiplexer 230 couples the first group of the primary device IO pins 201 to the test channels 221 and a scan test is performed. In this run, only a few devices pads are connected to the tester through 201. The remaining devices pins need the multiplexer 230 switch to connect to 202 Therefore, the same test pattern has to be executed for a second time while the multiplexer is switched such that the second group pins 202 are coupled to the test channels 221, as shown in diagram 260.
The diagram 240 illustrates the tester sequence for this scan test. The “scan in/out” boxes (e.g., 241 and 242) and “parallel” boxes (e.g., 243) represent the test sequencer. As illustrated by the box widths, the scan in/out operations need only a few tester channels (e.g., 241 and 242); while for the “parallel” launch/capture cycle many tester channels (e.g., 243) are needed.
The example in FIG. 2 demonstrates that, although the conventional multiplexing scan test approach reduces the requirement for the number of test channels in the tester, the associated capital cost saving is unfortunately achieved at the expense of multiplying scan test time. For instance, doubling the scan test time typically results in the overall test time increased by a factor of 10-30%, and consequently the test throughput is decreased by the same amount. Further, this multiplexing approach may offer less test coverage compared to a non-multiplexed solution because there will be corner paths that may require primary IO input data from both executions.